1. Field of the Invention
The invention relates to bus arbitration protocols, and more particularly, to a protocol including multiple arbiters for arbitrating access to a plurality of buses.
2. Description of the Related Art
The performance demands on personal computers are ever increasing. It has been determined that a major bottleneck in improving performance is the capability to perform input/output (I/O) operations. Processor speeds continue to increase at a great rate and memory speeds and architectures can partially keep pace. However, the speed of I/O operations, such as disk and local area network (LAN) operations, has not kept pace. The increasing complexity of video graphics used in personal computers is also demanding greater performance then can be conventionally provided.
Some of the problems were in the bus architecture used in IBM PC-compatible computers. The EISA architecture provided some improvement over the ISA architecture of the IBM PC/AT, but more performance was still required. To this end Intel Corporation, primarily, developed the Peripheral Component Interconnect (PCI) bus. The PCI bus is a mezzanine bus between the host or local bus in the computer, to which the processor and memory are connected, and the I/O bus, such as ISA or EISA. For more details on the PCI bus, reference to the PCI Standard Version 2.0, from the PCI Special Interest Group in care of Intel Corp., which is hereby incorporated by reference, is advised. The bus was designed to have a high throughput and to take advantage of the increasing number of local processors that support I/O functions. For example, most disk controllers, particularly SCSI controllers, and network interface cards (NICs) include a local processor to relieve demands on the host processor. Similarly, video graphics boards often include intelligent graphics accelerators to allow higher level function transfer. Typically these devices have the capability of operating as bus masters, to allow them to transfer data at the highest possible rates.
Because of the number of potential devices trying to be bus masters, an arbitration scheme is required. A common arbitration scheme is least-recently-used (LRU). In certain cases, such as described in application Ser. No. 07/955,499, entitled "Prioritization of Microprocessors in Multiprocessor Computer Systems," filed on Oct. 2, 1992, which is hereby incorporated by reference, the LRU scheme is modified so that the LRU of just the various requesters is utilized. This avoids potential deadlock conditions.
Another common type of arbitration scheme is the rotating priority scheme, where requesters are assigned highest priority on a rotating basis. In computer systems having a plurality of buses, such as those with a PCI bus and an EISA or ISA bus, a plurality of arbiters are required. It is thus desirable that an efficient arbitration scheme be developed for the plurality of arbiters for optimal usage of the plurality of buses.